This project grew out of the need to generate a linear crystal controlled ramp signal for the HP 8620C RF Sweep Oscillator. It is inspired by a previously published ramp generator design [1]. There are two problems with this design: it uses a non-standard 16.384MHz crystal oscillator; its ramp has zero fall/return/blank times.
To address the first issue, the ramp generator described here uses a standard 10MHz clock, so it can be integrated into an existing test setup. Second, most devices require a limited amount of time to return to their original state before starting a new scan. The designs shown in Figures 1 and 2 (see below) overcome these problems. The ramp generator part will be described first, as its requirements drive the design of the clock generator.
Ramp generator
At the heart of the ramp generator is a 12-bit digital-to-analog converter (DAC) driven by a binary counter. The DAC is of the discrete R-2R type as there was no suitable DAC IC at the time of development. This is driven by a set of AND gates (three 74HC08s), which in turn are driven by two 74HC393 dual 4-bit binary counters - and half of one of them is unused. The maximum possible count of 12 bits is 4096 states. A simplified schematic of the ramp generator is shown in Figure 1.
To determine the blanking time, the DAC outputs ramps only for the first 4,000 states. For the remaining 96 states, its output remains at 0V, which is enough time for the HP 8620C to return to the starting frequency and stabilize. During the ramp phase, the AND gate passes the counter output to the DAC. During the blanking phase, the AND gate is driven low, pulling the input of the DAC low and its output to 0V. The output of the counter is then monitored by a two-input OR gate (two 1N4148 diodes and a resistor) and a five-input NAND gate (74HC300 with three inputs tied together) and drives the AND gate's output during blanking public input. There is also an inverter consisting of a NOR gate (74HCO2) to generate a positive blanking pulse, which can then be used to modulate the oscilloscope's Z input.
The resistive diode switch at the output of the DAC is also enabled during the blanking phase, pulling the output of the DAC to 0V. During the ramp phase, the output of the DAC is amplified by an operational amplifier, which provides the 10V signal required by the HP 8620C.
The ramp generator can be switched between free-running and external triggering—as shown in the external trigger mode in Figure 1. In trigger mode, a set-reset latch consisting of two NOR gates detects the rising edge of the blanking output to reset the 12-bit counter. Only when an external trigger arrives will the set reset latch reset so that the 12-bit counter can start counting again.
Clock generator
The internal or external 10MHz crystal reference is split into 12 separate frequencies and selected by a 12-way rotary switch for feeding to the ramp generator. Since the ramp generator only generates ramp outputs for the first 4,000 states rather than 4,096 states, the standard divider ratios of 2, 5, and 10 for the 74HC390 dual-decimal counter can be used, as shown in Figure 2. The 74HC390 consists of two independent divide-by-2 and divide-by-5 counters configured as shown. The clock frequency of each output is noted in the figure along with its corresponding sweep time (in parentheses).
An exception to the above explanation is the 1ms scan time, which requires a 4MHz clock. Therefore, the first divider stage is a divide-by-2.5. This is achieved by utilizing the least significant bits of the divide-by-5 counter. For every five input pulses, it produces two output pulses: 000, 001, 010, 011, 100, 000, 001, 010, and 011, etc. The duty cycle of this 4MHz clock varies from cycle to cycle, which causes a slight jitter in the 1ms scan time, but this only manifests itself in the least significant bits of the ramp generator counter, so it doesn't matter. Alternative 2.5 dividers with 50% fixed duty cycle can be used, but are more complicated
Result
The measured output waveforms of the ramp output and blanking output are shown in the figure, and it can be seen that their exact period is 100ms and the ramp has high linearity.
The complete ramp generator is built using strip copper foil breadboards and mounted in an equipment box with an integrated power supply to build useful lab equipment.
